1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to the techniques for reducing chip package interactions caused by thermal mismatch between the chip and the package.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable base materials for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like. The individual integrated circuits are arranged in an array on the wafer, wherein most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economical constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In an attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with a low-k dielectric material, has become a frequently used alternative in the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors, and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to a reduced cross-sectional area. For this reason, traditional dielectrics, such as silicon dioxide (k>3.6) and silicon nitride (k>5), are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics, having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of sensitive dielectric materials, such as low-k dielectric layers, and their adhesion to other materials.
In addition to the problems of reduced mechanical stabilities of advanced dielectric materials having a dielectric constant of 3.0 and significantly less, device reliability may be affected by the provision of these materials during operation of sophisticated semiconductor devices due to an interaction between a chip and the package caused by a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly a contact technology may be used in connecting the package carrier to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a wire, in the flip chip technology, a respective bump structure may be formed on the last metallization layer, for instance comprised of a solder material, which may be brought into contact with respective contact pads of the package. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the last metallization layer and the contact pads of the package carrier. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the IO (input/output) capabilities which may be required for complex integrated circuits, such as CPUs, storage memories and the like. During the corresponding process sequence for connecting the bump structure with a package carrier, a certain degree of pressure and/or heat may be applied to the composite device to establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower lying metallization layers, which may typically include low-k dielectrics or even ultra low-k (ULK) dielectric materials, thereby significantly increasing the probability of creating defects by delamination of these sensitive materials due to reduced mechanical stability and adhesion to other materials. Moreover, during operation of the finished semiconductor device attached to a corresponding package substrate, significant mechanical stress may also occur due to a significant mismatch in the thermal expansion behavior of the silicon-based semiconductor chip and the package substrate, since, in volume production of sophisticated integrated circuits, economic constraints typically require the usage of specified substrate materials for the package, such as organic materials, which may typically exhibit a different thermal conductivity and a co-efficient of thermal expansion compared to the silicon chip. Consequently, a premature failure of the metallization system may occur, as will be described with reference to FIGS. 1a-1b in more detail.
FIG. 1a schematically illustrates a cross-sectional view of an integrated circuit 150 comprising a semiconductor die or chip 100 connected to a package substrate 170 substantially comprised of an organic material, such as appropriate polymer materials and the like, by means of a bump structure 160. The semiconductor chip 100 may typically comprise a substrate 101, for instance a silicon substrate or an SOI substrate, depending on the overall configuration of the circuit layout and performance of the integrated circuit 150. Furthermore, a silicon-based semiconductor layer 102 may typically be provided “above” the substrate 101, wherein the semiconductor layer 102 may comprise a very large number of circuit elements, such as transistors, capacitors, resistors and the like, as may be required by the desired functional behavior of the integrated circuit 150. As previously discussed, the ongoing shrinkage of critical dimensions of circuit elements may result in critical dimensions of transistors on the order of magnitude of 50 nm and significantly less in presently available sophisticated semiconductor devices produced by volume production techniques. Furthermore, the semiconductor chip 100 may comprise a metallization system 110, which, in advanced devices, may comprise a plurality of metallization layers, i.e., of device levels, in which metal lines and vias may be embedded in an appropriate dielectric material. As discussed above, at least a portion of the corresponding dielectric materials used in the various metallization layers may be comprised of materials of reduced mechanical stability in order to keep the parasitic capacitance of adjacent metal lines as low as possible. As previously explained, at least a portion of the bump structure 160 may be provided as a part of the metallization system 110, wherein corresponding bumps, for instance comprised of a solder material, may be provided on the very last metallization layer of the system 110. On the other hand, the package substrate 170 may comprise appropriately positioned and dimensioned contact pads (not shown), which may be brought into contact with the corresponding bumps in order to establish respective mechanical and electrical connections upon application of heat and/or mechanical pressure. Furthermore, the package substrate 170 may comprise any appropriate conductive lines in order to connect the bumps of the bump structure 160 with corresponding terminals, which may then establish an electrical interface to other peripheral components, such as a printed wiring board and the like. For convenience, any such conductive lines in the package substrate 170 are not shown.
During operation of the integrated circuit 150, heat may be generated within the semiconductor chip 100, for instance caused by the circuit elements formed in and above the semiconductor layer 102, which may be dissipated, for instance via the metallization system 110 and the bump structure 160 and/or via the substrate 101, depending on the overall thermal conductivity of the substrate 101. For example, the heat dissipation capability of SOI substrates may be significantly less compared to pure silicon substrates due to the reduced thermal conductivity of the buried insulating oxide layer, which may separate the semiconductor layer 102 from the remaining substrate material. Thus, a major heat dissipation path may be represented by the bump structure 160 and the package substrate 170. Consequently, a moderately high average temperature may be created in the semiconductor chip 100 and also in the package substrate 170 wherein, as previously discussed, a mismatch in the coefficient of thermal expansion between these two components may cause a significant mechanical stress. As is, for instance, indicated by arrows 103 and 173, the package substrate 170 may exhibit an increased thermal expansion compared to the semiconductor chip 100, wherein a corresponding mismatch may therefore result in a significant degree of thermal stress, in particular at the “interface” between the semiconductor chip 100 and the package substrate 170, that is, in particular the bump structure 160 and the metallization system 110 may experience significant shear forces caused by the thermal mismatch during the operation of the integrated circuit 150. Due to the reduced mechanical stability and the reduced adhesion of sophisticated dielectric materials, corresponding defects may occur which may affect the overall reliability of the integrated circuit 150.
FIG. 1b schematically illustrates an enlarged view of a portion of the metallization system 110 during a typical situation when operating the integrated circuit 150. As illustrated, the metallization system 110 may comprise a plurality of metallization layers, wherein, for convenience, two metallization layers 120 and 130 are illustrated. For example, the metallization layer 120 may comprise a dielectric material 121, in which corresponding metal lines 122 and vias 123 may be embedded. Similarly, the metallization layer 130 may comprise a dielectric material 131 and respective metal lines 132 and vias 133. Furthermore, typically, the metallization layers 120, 130 may comprise etch stop/capping layers 124, 134, respectively, which may be provided in the form of an appropriate material having desired characteristics with respect to etch stop capabilities, confining copper and the like. Moreover, as previously explained, at least some of the metallization layers in the metallization system 110 may comprise a sensitive dielectric material in the form of a low-k dielectric material or a ULK material which may exhibit a significantly reduced mechanical stability compared to other dielectrics, such as silicon nitride, silicon carbide, nitrogen-containing silicon carbide, which may frequently be used as the etch stop/capping layers 124, 134. Consequently, during operation of the integrated circuit, due to the different behavior with respect to thermal expansion, as indicated by arrows 103, 173 (FIG. 1a), a significant mechanical stress may be transferred into the metallization layers 120, 130, as indicated by 103A. Consequently, the mechanical stress 103A may also prevail in the dielectric materials 131 and 121, thereby inducing a more or less pronounced strained state, which may result in the creation of defects 121A, 131A, which may finally result in a certain degree of delamination from the lower lying materials 124, 134, respectively, since the adhesion of ULK dielectric materials, such as the materials 121, 131, to the etch stop/capping layers 124, 134 may be reduced compared to conventional dielectric materials, such as silicon dioxide and the like. Consequently, the resulting delamination may finally result in a premature failure of the metallization system 110, thereby contributing to a reduced overall reliability of the integrated circuit 150 (FIG. 1a).
The problem of a reduced reliability of sophisticated metallization systems is even further exacerbated in advanced process technologies in which the dielectric constant of the corresponding inter-metal dielectrics may further be reduced, while at the same time the dimensions of the corresponding chip areas may be increased in order to even further enhance the overall functionality of integrated circuits. On the other hand, the increased complexity of the overall circuit layout may also require an increase of the number of stacked metallization layers, as previously explained, which may additionally result in a reduced mechanical stability, thereby even further contributing to a reduced reliability of complex integrated circuits. Furthermore, providing the bump structure 160 (FIG. 1a) may result in moderately tight mechanical coupling of the package substrate and the semiconductor chip, which may therefore “efficiently” transfer the resulting mechanical stress into the metallization layers provided below the bump structure 160 so that the weak components, i.e., the low-k dielectric materials, may have to accommodate significant mechanical stress forces which may periodically occur, in particular when a cycled operational mode may be used during the operation of the integrated circuit 150.
For this reason, in conventional approaches with respect to performance driven metallization systems including sophisticated dielectric materials, the overall size of the semiconductor chip has to be restricted to appropriate dimensions so as to maintain the overall mechanical stress components at an acceptable level. In other cases, the number of metallization layers may be restricted, thereby also restricting the packing density and/or the complexity of the circuit layout. In still other conventional approaches, less sophisticated dielectric materials may be used in order to enhance the overall mechanical stability, thereby sacrificing performance of the integrated circuits.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.